14.1 A Leading-Edge 0.9um Pixel CMOS Image Sensor Technology with Backside Illumination: Future Challenges for Pixel Scaling (Invited), S.G. Wuu, C.C. Wang, B.C. Hseih, Y.L. Tu, C.H. Tseng, T.H. Hsu, R.S. Hsiao, S. Takahashi, R.J. Lin, C.S. Tsai, Y.P. Chao, K.Y. Chou, P.S. Chou, H.Y. Tu, L.Tran,
In this paper, a leading edge N65 0.9um pixel BSI technology using 300mm bulk silicon wafer is reported with process breakthroughs. Challenges to go beyond <0.9um pixel size are discussed.
TSMC在2010 IEDM(International Electron Device Meeting)受邀的文章
0.9um pixel是非常的小的size,把electric circuit造成的開口率降低算進去,真正的active area更小
sensor小雖然可以做更小面積,做更多畫素,但photon少,對光學的影響更大
BSI有較強的光接收能力,但不曉得0.9um是不是一樣無奈????
0.9um Pitch Pixel CMOS Image Sensor Design Methodology
K. Itonaga, et al. Sony Corporation
"We demonstrated the first ever 0.9um pitch pixel CMOS image sensor (CIS), and revealed the problems that are likely to be encountered in future device structures. We developed a set of guidelines for the design of high quantum efficiency (QE) CISs, and verified their validity by comparing the image quality of 0.9, 1.12, 1.4 and 1.75um CISs. in addition, we proposed a simple methodology to optimize more complicated submicron pitch CIS structures."
K. Itonaga, et al. Sony Corporation
"We demonstrated the first ever 0.9um pitch pixel CMOS image sensor (CIS), and revealed the problems that are likely to be encountered in future device structures. We developed a set of guidelines for the design of high quantum efficiency (QE) CISs, and verified their validity by comparing the image quality of 0.9, 1.12, 1.4 and 1.75um CISs. in addition, we proposed a simple methodology to optimize more complicated submicron pitch CIS structures."
連Sony也才2009年IEDM公佈0.9um pixel技術,TSMC就在2010年發表0.9um技術,而且還是BSI, 這叫BSI大廠Sony情何以堪
套一句Nikkei雜誌的話:
數位相機業界的一位高階經理表示：“關於BSI型CMOS感測器的量產，台積電(TSMC)的表 現應令人刮目相看。http://big5.nikkeibp.com.cn/news/semi/52668-20100805.html
by the way
TSMC 與OmniVision合作BSI(BackSide Illumination)
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